By Steve Leibson
Microprocessor cores used for SOC layout are the direct descendents of Intel's unique 4004 microprocessor. simply as packaged microprocessor ICs fluctuate extensively of their attributes, so do microprocessors packaged as IP cores. despite the fact that, SOC designers nonetheless evaluate and choose processor cores the best way they formerly in comparison and chosen packaged microprocessor ICs. the massive challenge with this feature approach is that it assumes that the legislation of the microprocessor universe have remained unchanged for many years. This assumption isn't any longer valid.
Processor cores for SOC designs should be way more plastic than microprocessor ICs for board-level method designs. Shaping those cores for particular purposes produces far better processor potency and masses reduce approach clock charges. jointly, Tensilica's Xtensa and Diamond processor cores represent a family members of software-compatible microprocessors overlaying an incredibly broad functionality variety from uncomplicated keep watch over processors, to DSPs, to 3-way superscalar processors. but all of those processors use an analogous software-development instruments in order that programmers acquainted with one processor within the kinfolk can simply swap to another.
This publication emphasizes a processor-centric MPSOC (multiple-processor SOC) layout kind formed by means of the realities of the 21st-century and nanometer silicon. It advocates the project of initiatives to firmware-controlled processors every time attainable to maximise SOC flexibility, reduce energy dissipation, lessen the scale and variety of hand-built good judgment blocks, cut back the linked verification attempt, and reduce the general layout threat.
· a necessary, no-nonsense consultant to the layout of 21st-century mega-gate SOCs utilizing nanometer silicon.
· Discusses ultra-modern key concerns affecting SOC layout, according to author's a long time of private event in constructing huge electronic structures as a layout engineer whereas operating at Hewlett-Packard's laptop computing device department and at EDA computing device pioneer Cadnetix, and protecting such themes as an award-winning expertise journalist and editor-in-chief for EDN journal and the Microprocessor Report.
· Explores conventionally authorised barriers and perceived limits of processor-based method layout after which explodes those man made constraints via a clean outlook on and dialogue of the distinctive talents of processor cores designed in particular for SOC design.
· Thorough exploration of the evolution of processors and processor cores used for ASIC and SOC layout with a glance at the place the has come from, and the place it truly is going.
· Easy-to-understand reasons of the services of configurable and extensible processor cores via an in depth exam of Tensilica's configurable, extensible Xtensa processor middle and 6 pre-configured Diamond cores.
· the main accomplished evaluation on hand of the sensible points of configuring and utilizing a number of processor cores to accomplish very tough and impressive SOC fee, functionality, and gear layout pursuits.
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Additional resources for Designing SOCs with Configured Cores: Unleashing the Tensilica Xtensa and Diamond Cores
As a result, it's likely that microprocessors and software tools evolved more quickly than if the developments had remained more closely linked. However, this split has also produced a particular style of system design that is now limiting the industry's ability to design advanced systems. SOC designers compare and select processor cores the way they previously compared and selected packaged microprocessor ICs. They look at classic, time-proven figures of merit such as clock rate, main-bus bandwidth, cache-memory performance attributes, and the number of available thirdparty software-development tools to compare and select processors.
The trick is to build a fast system. mSeymour Cray Academic researchers, system-on-chip (SOC) designers, and ASIC and EDA vendors are in a fair a m o u n t of agreement as to what must be done to reduce SOC design risks. SOC designs m u s t become flexible enough to a c c o m m o d a t e design changes brought on by design errors, spec changes, standards changes, and competitive market forces. Designing additional flexibility into an SOC allows one chip design to serve several products and multiple product generations.
A split between the processor developers and tool developers opened and grew. Processor developers preferred to focus on hardware architectural advances and tool developers focused on compiler advancements. Processor developers would labor to produce the next great processor architecture and, after the processor was introduced, software-tool developers would find ways to exploit the new architectural hardware to produce more efficient compilers. In one way, this split was very good for the industry.
Designing SOCs with Configured Cores: Unleashing the Tensilica Xtensa and Diamond Cores by Steve Leibson