By Alexander Biedermann
Alexander Biedermann provides a usual hardware-based virtualization method, which can rework an array of any off-the-shelf embedded processors right into a multi-processor method with excessive execution dynamism. in accordance with this process, he highlights thoughts for the layout of strength acutely aware structures, self-healing platforms in addition to parallelized structures. For the latter, the radical so-called Agile Processing scheme is brought by means of the writer, which allows a unbroken transition among sequential and parallel execution schemes. The layout of such virtualizable platforms is extra aided by way of advent of a committed layout framework, which integrates into present, advertisement workflows. for that reason, this booklet offers accomplished layout flows for the layout of embedded multi-processor systems-on-chip.
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Extra info for Design Concepts for a Virtualizable Embedded MPSoC Architecture: Enabling Virtualization in Embedded Multi-Processor Systems
Although one can clearly derive from the Figure that the design is far from exceeding the logic resources available on the FPGA, expanding the design to feature more than three processors leads to unresolvable routing constraints. This is caused by the interconnection of tasks and processors. An overlay in dark grey depicts the connectivity of the design. As every task has to be connected to each processor, a high wiring complexity is caused by the employed multiplexer structures. As this limits scalability of the solution, the following section will introduce a sophisticated task-to-processor interconnection scheme.
Is composed of bindings Bi . Note that in a multi-processor system featuring the Virtualization Layer, a task does not have to be bound to a processor all the time. Instead, a task may be halted by the virtualization procedure and may then remain disconnected from a processor for an arbitrary amount of time. Furthermore, processors do not necessarily have to be bound to a task. These two features enable transparent sharing of a processor resource, cf. 6. 8: A Multi-Processor System featuring the Virtualization Layer.
2 Virtualization for Embedded Multi-Processor Architectures 23 Algorithm 4 Phase 3 of Virtualization Procedure: Context Restauration. Require: A halted task t, its context inside the TCM of its virtbridge, a processor p routed to t via t’s virtbridge. Ensure: Seamless continuation of t’s execution. i. , t had already been active at least once 1: if TCM of t is not empty then 2: for all Status registers of p do 3: Inject instruction sequence that will set p’s status register based on value saved inside TCM 4: end for 5: for all General purpose registers of p do 6: Inject load word immediate via CIL into p that reads from t’s TCM into p’s register 7: end for 8: Detach TCM from p’s data memory interface and attach t’s data memory 9: Inject branch instruction to program counter address saved in TCM 10: Detach CIL from p’s instruction memory interface and attach t’s instruction memory 11: else i.
Design Concepts for a Virtualizable Embedded MPSoC Architecture: Enabling Virtualization in Embedded Multi-Processor Systems by Alexander Biedermann