By Panagiotis Dimitrakis
This ebook describes the fundamental applied sciences and operation rules of charge-trapping non-volatile thoughts. The authors clarify the equipment physics of every equipment structure and supply a concrete description of the fabrics concerned in addition to the elemental houses of the know-how. sleek fabric homes used as charge-trapping layers, for brand new purposes are introduced.
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Extra info for Charge-Trapping Non-Volatile Memories: Volume 1 – Basic and Advanced Devices
2007). The new CTM cell architecture is shown in Fig. 22c and the related energy band diagram is presented in Fig. 22d. The main advantage of BE-SONOS devices is the enhanced injection of hole charges. From the manufacturing point of view, CTMs have a better scalability than Flash. The SONOS-like device provides very low power cell and can be used in either a moderate density NOR architecture with isolated source lines or a highdensity, multi-byte, NAND architecture. A unique feature of SONOS lies in their radiation hardness for military and space applications (White 2000, 2006).
1. The coupling to the floating gate is typically expressed as a coupling coefficient given by: Cn /n ¼ Xi¼n 1 Ci ð2:1Þ The floating gate voltage is given by: V fg ¼ i¼n X /i V i ð2:2Þ 1 The FG potential is dependent on the voltage applied to a given coupling capacitance and the ratio (α) of the given capacitance to the total capacitance from all sources. A large voltage and a large ratio results in a larger voltage coupled on to the FG. 1 Key NAND historical milestones Year 1967 Inventor and company Kahng et al.
9 Planar floating gate options showing the control gate (CG), blocking dielectric (BD), trapping layer (nitride, nanodots, and a thin floating gate), and tunnel oxide various alternative approaches and discusses the planar cell technology that successfully overcame these issues to enable mass production of a scaled 16 and 20 nm cell. One key advantage of a planar cell is some relief from the floating gate to floating gate interference as shown in Fig. 8 simply because the planar cell is thin reducing the capacitance.
Charge-Trapping Non-Volatile Memories: Volume 1 – Basic and Advanced Devices by Panagiotis Dimitrakis