Download PDF by Manish Verma, Peter Marwedel: Advanced Memory Optimization Techniques for Low-Power

February 1, 2018 | Microprocessors System Design | By admin | 0 Comments

By Manish Verma, Peter Marwedel

ISBN-10: 1402058969

ISBN-13: 9781402058967

ISBN-10: 1402058977

ISBN-13: 9781402058974

The layout of embedded platforms warrants a brand new point of view as a result of the following purposes: to start with, gradual and effort inefficient reminiscence hierarchies have already turn into the bottleneck of the embedded platforms. it really is documented within the literature because the reminiscence wall challenge. Secondly, the software program working at the modern embedded units is changing into more and more complicated. it's also good understood that no silver bullet exists to resolve the reminiscence wall challenge. hence, this booklet explores a collaborative strategy by means of offering novel reminiscence hierarchies and software program optimization ideas for the optimum usage of those reminiscence hierarchies. Linking reminiscence structure layout with memory-architecture conscious compilation leads to speedy, energy-efficient and timing predictable reminiscence accesses. The overview of the optimization ideas utilizing real-life benchmarks for a unmarried processor approach, a multiprocessor system-on-chip (SoC) and for a electronic sign processor procedure, reviews major discount rates within the strength intake and function development of those structures. The e-book provides quite a lot of optimizations, gradually expanding within the complexity of research and of reminiscence hierarchies. the ultimate bankruptcy covers optimization strategies for purposes which include a number of strategies present in most up-to-date embedded units. complex reminiscence Optimization ideas for Low strength Embedded Processors is designed for researchers, complier writers and embedded procedure designers / architects who desire to optimize the strength and function features of the reminiscence subsystem.

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Additional resources for Advanced Memory Optimization Techniques for Low-Power Embedded Processors

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Statistics about the number and type of accesses to the background data memory and the scratchpad memory are collected. These statistics and the energy model are used to compute the energy dissipated by the data memory subsystem of the M5 DSP. The benchmarks for M5 DSP based systems are obtained from the UTDSP [73] benchmark suite. 4 Non-Overlayed Scratchpad Allocation Approaches for Main / Scratchpad Memory Hierarchy In this first chapter on approaches to utilize the scratchpad memory, we propose two simple approaches which analyze a given application and select a subset of code segments and global variables for scratchpad allocation.

Energy Comparison of Scratchpad Allocation Approaches detection and dsp benchmarks, respectively. The Frac. SA approach is allowed to allocate one memory object across the boundary of the scratchpad such that it is partially present in the scratchpad space and partially in the main memory space. Therefore, the approach always utilizes the entire scratchpad space to allocate memory objects. This should result in more energy efficient scratchpad allocations for the Frac. SA approach than those for the SA approach.

The goal of the proposed approaches is to minimize the total energy consumption of the system with a memory hierarchy consisting of an L1 scratchpad and a background main memory. The chapter presents an ILP based non-overlayed scratchpad allocation approach and a greedy algorithm based fractional scratchpad allocation approach. The presented approaches are not entirely novel as similar techniques are already known. They are presented in this chapter for the sake of completeness, as the advanced scratchpad allocation approaches presented in the subsequent chapters improve and extended these approaches.

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Advanced Memory Optimization Techniques for Low-Power Embedded Processors by Manish Verma, Peter Marwedel


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